Intel Chief Executive Lip-Bu Tan has framed the AI hardware race as a systems-engineering challenge rather than a contest over individual chip benchmarks, placing memory, networking, packaging, cooling, manufacturing and execution alongside raw compute performance.
In a long-form interview on Intel’s product and foundry strategy, Tan said AI is making power consumption, bandwidth and available computing capacity direct limits on how quickly applications can expand. The shift places semiconductor design closer to the commercial economics of AI: a model may be capable in theory, but its deployment can be constrained by the cost of moving data, supplying power and removing heat from densely packed equipment.
Tan’s comments arrive as semiconductor demand accelerates around AI infrastructure. World Semiconductor Trade Statistics expects global chip sales to reach $975 billion in 2026, bringing the industry close to the $1 trillion annual level earlier than many prior forecasts had anticipated.
Ai workloads are moving bottlenecks beyond accelerators
The first wave of generative AI infrastructure focused heavily on training large models with high-performance accelerators. Tan said the market is now dealing with a broader set of workloads, including inference, AI agents and physical AI systems that interact with machines and real-world environments.
Those uses place pressure on parts of a computing system that receive less attention than specialized AI chips. Inference requires serving models repeatedly and quickly, often with tight latency requirements. Agent-based software can generate many smaller, interconnected tasks that need scheduling, memory access and data movement. Physical AI adds sensor data, control systems and real-time processing requirements.
Tan said CPUs remain central to that workload mix even as accelerators take on more AI-specific calculations. CPUs continue to process data, schedule tasks and run the software environment surrounding AI models. That leaves Intel with an argument for maintaining a strong role in AI data centers despite the rapid expansion of accelerator-led infrastructure.
The constraint is increasingly how efficiently components work together. A fast processor can spend time waiting when memory cannot supply data quickly enough, while a system with abundant compute can face limits in networking capacity or thermal headroom. For operators building large AI clusters, those bottlenecks can determine how much usable performance they receive from equipment already installed.
Memory and cooling are becoming design priorities
Tan identified memory bandwidth, capacity and power consumption as tightening constraints in AI systems. Modern AI workloads move and retain enormous volumes of data, and transferring that information can consume substantial energy. The challenge is pushing chip designers to reconsider how processors and memory are arranged within a server and package.
Intel is researching CPU-and-memory stacking and alternative memory architectures, Tan said, though he did not provide product specifications or a release schedule. Stacked designs could shorten the distance data travels between computing and memory components, potentially improving bandwidth and reducing energy used for data movement.
Intel has also hired former SK hynix chief executive Lee Seok-hee. Tan did not outline specific programs attached to the appointment, but the hire adds memory-sector experience as Intel evaluates its system-level approach.
Heat management is another increasingly expensive part of the infrastructure equation. Tan pointed to the industry’s movement from air cooling toward liquid cooling, with microfluidic cooling under development as a more advanced approach. Microfluidic techniques aim to bring coolant far closer to heat-generating components, addressing the rising thermal density created by powerful processors placed in tightly configured systems.
The company is also tracking a transition from electrical interconnects toward photonics, which uses light to transmit data. Optical links can move large volumes of information over distance with different power and bandwidth characteristics than traditional copper-based connections. Tan also cited glass substrates and other materials as areas of interest, reflecting the extent to which AI demand is reaching into chip packaging and materials science.
Intel ties product strategy to foundry execution
Tan said Intel intends to retain a vertically integrated model spanning product design, advanced packaging and wafer manufacturing. The structure would allow the company to coordinate decisions across different layers of the system rather than treating chip architecture, packaging and fabrication as separate problems.
That approach also sets a demanding operational test. Intel must improve product competitiveness and manufacturing delivery at the same time, Tan said. Strong processor designs have limited value if manufacturing schedules slip or yields are weak, while a capable fabrication operation needs competitive products and external customers to justify the capital required for leading-edge production.
The company’s emphasis on integration comes after Intel lost ground during earlier technology transitions. Tan said Intel missed major shifts around mobile internet, cloud computing and AI. He described plans to expand its engagement with universities, AI laboratories, venture firms and startups, seeking earlier signals about technical changes that should influence product priorities and internal resource allocation.
Tan’s own record has shaped that management view. He recalled joining electronic-design-automation company Cadence when its shares traded at roughly $2.42. He initially accepted an interim chief executive role for three months but remained for 15 years. During that period, he said he responded to around 300 employee emails a day and set processes intended to address customer complaints within 24 hours.
Capital is following the infrastructure buildout
Tan said global semiconductor revenue is nearing $1 trillion earlier than expected, underscoring the scale of capital moving into the sector. He has invested in chip companies since 1987 and said he has backed nearly 550 companies over his career.
He cited SambaNova as an example from his venture history, saying Celesta invested an initial $2 million in the AI hardware company in 2017 at an estimated valuation of about $12 million. Tan said SambaNova is now pursuing an F-round funding raise of roughly $800 million to $1 billion, referring to the size of the proposed financing rather than its valuation.
For cryptocurrency infrastructure operators, the interview offers a useful distinction between AI data-center requirements and the needs of mining or blockchain-validation hardware. Liquid cooling, high-bandwidth memory and optical networking can be valuable in particular high-density deployments, but they are not universal upgrades that automatically improve returns. Equipment decisions depend on the workload, electricity costs, facility design, network architecture and the economics of the protocol being operated.
Tan’s system-focused framework nevertheless captures the pressure spreading through high-performance computing: future gains will increasingly depend on balancing compute with the physical infrastructure needed to feed it, connect it and keep it cool.
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