SMIC matches TSMC 7nm with DUV

China’s leading foundry, SMIC, has achieved transistor densities comparable to Taiwan’s 7‑nanometer technology using only deep ultraviolet (DUV) lithography, according to a new teardown report by SemiAnalysis. The firm found SMIC’s N+3 process reached 113.4 million transistors per square millimeter, slightly exceeding the 107.7 MTr/mm² reported for TSMC’s N6 node. The process also features a minimum metal pitch of 32.5 nanometers, narrower than Intel’s 36‑nanometer 18A.

Higher density comes with rising complexity and cost

The report highlights that these gains come at a significant cost. Engineers relied on self‑aligned quadruple patterning (SAQP) rather than the simpler double patterning used by Taiwanese manufacturers, increasing both process complexity and production expenses. Physical analysis also revealed inverted‑trapezoid structures in metal trenches, pointing to the technical limits of multi‑patterned DUV fabrication.

Huawei chip shows modest real‑world performance gains

Huawei’s Kirin 9030 chip, built on SMIC’s N+3 node and used in the Mate 80 Pro, demonstrates the practical outcome of these advances. While maintaining a die size of about 140 square millimeters, the chip integrates more CPU, GPU, and NPU resources. Performance tests show its Maleoon 935 GPU roughly matches the Snapdragon 8+ Gen 1 from 2022, while CPU performance aligns with the 2021 Arm Cortex‑X2 generation and trails Apple’s latest M5 by a wide margin.

SemiAnalysis notes that design improvements alone cannot fully overcome limitations imposed by older manufacturing nodes, leaving a persistent performance gap.

Huawei turns to 3d stacking strategy

To address these constraints, Huawei is advancing a 3D chip‑stacking approach known as LogicFolding. This strategy aims to vertically stack logic components to boost performance and efficiency. Under its roadmap, Huawei targets increasing core frequencies from 2.75 GHz to 5 GHz by 2031 and achieving an effective density of 295 MTr/mm², comparable to a projected 14‑angstrom class.

This is expected to be enabled by hybrid bonding techniques that shorten interconnect distances and reduce signal delay.

New metrics reshape how chip density is measured

SemiAnalysis notes that 3D stacking introduces new ways of evaluating chip density. For comparison, AMD’s MI450X, which integrates N2 and N3P nodes, could theoretically reach 460.2 MTr/mm² under similar 3D measurement methods. This suggests traditional node comparisons may become less relevant as multi‑die architectures evolve.

Export restrictions shift, not stop, China’s progress

The report concludes that export controls have redirected China’s semiconductor development rather than halted it. SMIC’s manufacturing expertise is being shared with Hua Hong, while domestic chip designers gain exposure to advanced nodes. At the same time, local electronic design automation tools are being developed in collaboration with Beijing University to support 3D chip design.

Mixed memory sourcing highlights partial self‑reliance

Teardown findings show a mix of domestic and foreign components. The Kirin 9030 Pro uses Samsung LPDDR5X‑9600 memory, while the Pro Max variant includes DRAM from ChangXin Memory Technologies, marking an early use of Chinese memory in premium smartphones. However, domestic DRAM remains one to two generations behind South Korean competitors.

Costs rise as China pushes semiconductor independence

SemiAnalysis indicates that while China’s approach expands technical know‑how, it significantly increases manufacturing costs and reduces efficiency. Some estimates suggest the Kirin 9030 may be produced at an operating loss due to its complexity. This push is part of a broader plan to scale domestic AI chip production rapidly and build a self‑sufficient technology ecosystem.

Global chip prices add further pressure

At the same time, TSMC is reportedly considering price increases of up to 15% for its 3nm wafers in the second half of 2026, potentially lifting costs from around $20,000 to $23,000 per wafer. Rising demand from AI applications and inflationary pressures are driving these increases.

Market and cost pressures converge

The combination of higher manufacturing costs and broader market uncertainty is creating a challenging environment. With sentiment indicators such as the Fear & Greed Index signaling extreme caution following recent market declines, traders are facing tighter conditions while the cost of high‑performance hardware continues to climb.

Strategic implications for hardware buyers

For companies reliant on large‑scale computing infrastructure, the current environment is forcing a reassessment of spending priorities. With next‑generation hardware becoming more expensive, the focus may shift toward extending the usable life of existing systems and optimizing overall operational efficiency rather than pursuing continuous upgrades.

Energy costs and total system efficiency are likely to become more critical factors, reshaping how firms approach hardware investment in the coming years.